Xilinx 編譯指令:`define,`ifdef

//這樣的程式只會跑 c<=a+b 那一段，而不會跑c<=2,除非拿掉`define full
`define full
module top(
input rst,
input clk,
input [width-1:0] a,
input [width-1:0] b,
output reg [width:0] c
    );

parameter width=1;
`ifdef full
always@(posedge clk or posedge rst)begin
if(rst)
c<=0;
else
c<=a+b;
end
`else
always@(posedge clk or posedge rst)begin
if(rst)
c<=0;
else
c<=2;
end
`endif

endmodule